Electrical engineers at the University of California, Irvine have developed a new wireless transceiver that operates at radio frequencies up to 140 gigahertz. This technology achieves data speeds comparable to those of fiber-optic cables and could support future 6G and FutureG wireless protocols.
The device, created by researchers in UC Irvine’s Samueli School of Engineering, uses a unique architecture that combines digital and analog processing. The result is a silicon chip system with both transmitter and receiver components, capable of handling digital signals more quickly and efficiently than previous technologies.
Details of the invention are described in two papers published in the IEEE Journal of Solid-State Circuits this month. One paper discusses the “bits-to-antenna” transmitter, while the other focuses on the “antenna-to-bits” receiver.
“We call this technology a ‘wireless fiber patch cord’ because it offers the blistering speed of fiber optics without the physical cables,” said Payam Heydari, director of UC Irvine’s Nanoscale Communication Integrated Circuits Labs and senior author of both papers. “By operating in the F-band – a frequency range well above current 5G standards — we can offer massive bandwidths that will transform how machines, robots and data centers communicate.”
Heydari explained that his team began developing the bits-to-antenna concept in 2020 after identifying limitations in traditional mixed-signal chip architectures, which rely heavily on energy-intensive data converters. He stated: “We realized that to reach the elusive 100-gigabit-per-second milestone — which is 100 times the speed of current wireless devices – without melting the chip, we had to fundamentally rethink the circuit topology. We envisioned novel, all-analog architectures that could overcome the severe power trade-offs plaguing high-speed designs.”
The team determined that as speeds increased, it was necessary to shift more processing into the analog domain to avoid inefficiencies found in standard 5G chips. Heydari noted: “If we stuck to traditional methods, the battery life of next-generation devices would vanish in minutes. Our group’s answer is a transceiver that leapfrogs over current limitations by performing complex calculations in the analog domain, rather than the power-hungry digital domain.”
The transceiver can operate at 120 gigabits per second—enough to transfer several 4K movies almost instantly.
Zisong Wang, former UC Irvine doctoral researcher and lead author of one paper who now works at Marvell Technology Inc., commented: “The Federal Communications Commission and 6G standards bodies are looking at the 100-gigahertz spectrum as the new frontier. But at such speeds, conventional transmitters that create signals using digital-to-analog converters are incredibly complex and power-hungry and face what we call a DAC bottleneck.” He explained that their new transmitter avoids this issue by building signals directly in the radio-frequency domain using three components: “It’s like packing a suitcase perfectly before leaving the house rather than trying to organize it while running to the airport,” Wang said.
Mohammad Oveisi, a UC Irvine doctoral student involved with another aspect of development, explained that their method—RF-domain 64QAM—allows for efficient high-data-rate transmission without overheating devices. This capability is important for supporting emerging technologies such as internet-connected products, autonomous vehicles, and AI edge computing.
Youssef Hassan, lead author on one paper and now with Qualcomm, discussed challenges faced by traditional receivers: “Traditional receivers struggle to catch such fast data without using massive, energy-draining components called analog-to-digital converters. Moore’s law suggests we can just make transistors smaller to go faster, but at these extreme speeds, we hit a physical wall known as the sampling bottleneck. Digitizing a 120-Gbps signal typically requires massive analog-to-digital converters that burn watts of power, far too much for a smartphone.”
To address this problem instead of increasing hardware demands further, Hassan said: “We developed a technique called hierarchical analog demodulation. By breaking the signal down hierarchically in the analog domain, peeling apart the complex data layers before they’re digitized, we extract the data using a fraction of the power typically required.” The receiver chip uses only 230 milliwatts of power thanks to its fabrication process.
Heydari highlighted additional benefits beyond high-frequency transmission: mass production is possible at lower cost due to its architecture. This could enable widespread use across various sectors. He added: “Our innovation eliminates the need for miles of complex copper wiring inside data centers. Data farm operators can do ultrafast wireless links between server racks, saving considerable money on hardware, cooling and power.”
He also pointed out that routine semiconductor manufacturing processes were used during development.
Funding for this research came from the U.S. Department of Defense Microelectronics Commons program.
